Refer to:
https://github.com/schoeberl/chisel-lab/blob/master/Setup.md
https://com-lihaoyi.github.io/mill/mill/Intro_to_Mill.html
https://github.com/OpenXiangShan/XiangShan
1.
#preinstall
apt install openjdk-8-jdk git make
2.
#install python 3.7:
http://fatalfeel.blogspot.com/2019/12/ai-with-cuda-install-step-and-yolov3-in.html
label: install python 3.7 + pip3 + labelimg + yolov3
Do step 1~9
3.
#install scala tool:
https://www.scala-sbt.org/download.html
echo "deb https://repo.scala-sbt.org/scalasbt/debian all main" | sudo tee /etc/apt/sources.list.d/sbt.list
echo "deb https://repo.scala-sbt.org/scalasbt/debian /" | sudo tee /etc/apt/sources.list.d/sbt_old.list
curl -sL "https://keyserver.ubuntu.com/pks/lookup?op=get&search=0x2EE0EA64E40A89B84B2DF73499E82A75642AC823" | sudo apt-key add
sudo apt update
sudo apt install sbt
4.
#download IntelliJ IDEA Community Edition 2019.3.5
https://www.jetbrains.com/idea/download/other.html
extract to /opt/idea-IC-193.7288.26
5.
#download Linux Self Extracting Web Installer
Xilinx_Unified_2019.2_1106_2127_Lin64.bin
https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/vivado-design-tools/archive.html
run bin file and then select [Vivado HL_WebPACK]
6.
run /opt/idea-IC-193.7288.26/bin/idea.sh
File -> Settings -> Plugins
search [scala] and install it.
File -> Open -> ~/chisel-lab-master/lab1
right click Hello.scala -> Debug
It will auto generate ~/chisel-lab-master/lab1/Hello.v
when first debug meet
Error: Could not find or load main class
close project and reopen will be ok
7.
#lab1 in Vivado 2019.2.1
File -> Project -> New project -> RTL project
Project name: lab1
Project location: ~/chisel-lab-master/lab1
Create project subdirectory - uncheck
Add Sources: Hello.v
Add Constraints: Basys3Hello.xdc
Select first part: xa7a12tcpg238-2I
open view [Flow Navigator]
SIMULATION: Run Simulation(left click) -> Run Behavioral Simulation
RTL ANALYSIS: Open Elaborated Design -> Schematic (see the circuit)
8.
#option lab1 in Vivado 2019.2.1
File -> Project -> New project -> Post-synthesis project
Project name: lab1
Project location: ~/chisel-lab-master/lab1
Create project subdirectory - uncheck
Add Sources: Hello.v
Add Constraints: Basys3Hello.xdc
After create project will popup
[There is no top module specified for synthesis...specify one now?]
press [OK] -> click [...] -> select module name -> [OK]
open view [Flow Navigator]
NETLIST ANALYSIS: Report power (left click)
9.
#risc-v cpu XiangShan project, I use root login ubuntu 16.04
apt install verilog
sh -c "curl -L https://github.com/com-lihaoyi/mill/releases/download/0.9.9/0.9.9 > /usr/local/bin/mill && chmod +x /usr/local/bin/mill"
mill version
mkdir -p /root/riscv_cpu
cd /root/riscv_cpu
git clone --recursive https://github.com/OpenXiangShan/NEMU.git
git clone --recursive https://github.com/OpenXiangShan/nexus-am.git
git clone --recursive https://github.com/OpenXiangShan/XiangShan.git
git clone --recursive https://github.com/verilator/verilator
#absolute path
export NEMU_HOME="/root/riscv_cpu/NEMU"
export AM_HOME="/root/riscv_cpu/nexus-am"
export NOOP_HOME="/root/riscv_cpu/XiangShan"
cd verilator
autoconf
./configure
make -j8 && make install
cd /root/riscv_cpu/XiangShan
make init
gedit /root/riscv_cpu/XiangShan/build.sc
#find all
-Xmx64G
#change to
-Xmx16384m (depend on you PC ram size)
#generate .v
make verilog -j8
(after message "Done elaborating." will go to compile please wait)
#simulation
make emu CONFIG=MinimalConfig SIM_ARGS=--disable-log EMU_THREADS=2 -j8
./build/emu -b 0 -e 0 -i ./ready-to-run/coremark-2-iteration.bin --diff ./ready-to-run/riscv64-nemu-interpreter-so
10.
#XiangShan in IntelliJ IDE
export NEMU_HOME="/root/riscv_cpu/NEMU"
export AM_HOME="/root/riscv_cpu/nexus-am"
export NOOP_HOME="/root/riscv_cpu/XiangShan"
cd /root/riscv_cpu/XiangShan
mill mill.scalalib.GenIdea/idea
run /opt/idea-IC-193.7288.26/bin/idea.sh
open directory /root/riscv_cpu/XiangShan
File -> Settings -> Build -> Build Tools -> Maven -> Importing
VM options for importer: -Xmx16384m
JDK for importer: 1.8
File -> Settings -> Build -> Build Tools -> sbt
Maximum heap size, MB: 16384
[checked] Automatically import this project on changes in build script files
File -> Settings -> Build -> Compiler -> Scala Compiler -> Scala Compiler Server
JVM maximum heap size, MB: 16384
JVM options: -server -Xss256m
File -> Settings -> Build -> Debugger
[checked] Friendly display of Scala collections in debugger
[checked] Do not expand Streams and Views
Collection start index: 0
Collection end index: 64
File -> Project Structure -> Project Settings -> Project
Project SDK: 1.8 (your java version)
[OK]
File -> Invalidate Caches / Restart
[Invalidate and Restart]
Build -> Rebuild Project
11.
right click file ~/riscv_cpu/XiangShan/src/test/scala/top/SimTop.scala
[Create] -> Configuration -> Environment variables: JAVA_TOOL_OPTIONS=-Xmx16384m -Xss256m
right click file ~/riscv_cpu/XiangShan/src/test/scala/top/SimTop.scala
[Run]
demo: https://www.mediafire.com/view/cirfs38wph9xtpu/IntelliJ.png
12.
#XiangShan for "Vivado HL System Edition" 2019.2.1
File -> Project -> New project -> RTL project
Project name: XSTop
Project location: ~/riscv_cpu/XiangShan/build
Create project subdirectory - uncheck
Add Sources:
XSTop.v
plusarg_reader.v
tsmc28_sram.v
Add Constraints: None
Select last part: xqzu29dr-ffrf1760-1M-m
#or
Select last board: Zynq UltraScale+ RFSoC ZCU1285 Characterization Kit
open view [Flow Navigator]
RTL ANALYSIS: Open Elaborated Design -> Schematic (see the circuit)
demo: https://www.mediafire.com/view/83dtz6uhwve53m1/rsic-v_cpu.png
13.
In the future
For some case, we can use AI design the Risc-V chip
Simulation -> Correct answer score + predict run time
Real value -> Correct answer score + shortest run time
Select the Cross Entropy loss + MSE loss
14.
Chisel sample on iCESugar
https://pingu98.wordpress.com/2019/04/08/how-to-build-your-own-cpu-from-scratch-inside-an-fpga
https://github.com/wuxx/icesugar (toolchain)
https://github.com/ekiwi/icesugar-chisel
https://github.com/wuxx/VexRiscv
https://zhuanlan.zhihu.com/p/133913104
////////////////////////////////////////////////////////
///////////////////////Tutorial/////////////////////
////////////////////////////////////////////////////////
(a) chisel language
https://zhouyuqian.com/2021/05/24/chisel-start
https://www.cnblogs.com/JamesDYX/archive/2018/12.html
(b) xdc constraints
https://www.codetd.com/en/article/12700925
https://www.eda365.com/article-147310-1.html
(c) Arbiter
https://www.allaboutcircuits.com/technical-articles/simple-priority-arbiter-allocating-resources-embedded-systems-vhdl-logism
https://zhuanlan.zhihu.com/p/390964916
(d) ALU (Arithmetic Logic Unit) example
import chisel3._
import chisel3.iotesters.PeekPokeTester
import Chisel.{INPUT, OUTPUT, UInt, Mux}
class AddSub extends Module {
val io = IO(new Bundle {
val in0 = UInt(INPUT, 8)
val in1 = UInt(INPUT, 8)
val sel = Input(Bool())
val out = UInt(OUTPUT, 8)
})
val in2_inv = Mux(io.sel, ~io.in1, io.in1)
io.out := io.in0 + in2_inv + io.sel
}
class TesterSimple(dut: AddSub ) extends PeekPokeTester(dut)
{
poke(dut.io.sel, 0.U) //0 add
poke(dut.io.in0, 7.U) //set value
poke(dut.io.in1, 6.U)
step (1) //run 1 cycle clock
println("Result is: " + peek(dut.io.out).toString) //get value and print
poke(dut.io.sel, 1.U) //1 sub
poke(dut.io.in0, 7.U) //set value
poke(dut.io.in1, 6.U)
step (1)
println("Result is: " + peek(dut.io.out).toString)
}
object Main_AddSub extends App {
//test result
chisel3.iotesters.Driver(() => new AddSub())
{
c => new TesterSimple (c)
}
//make .v
(new chisel3.stage.ChiselStage).emitVerilog(new AddSub())
}
(e) register file
https://www.cs.cornell.edu/courses/cs3410/2019sp/schedule/slides/06-cpu-pre-bw.pdf
http://stenlyho.blogspot.com/2008/08/register-file-in-verilog.html
https://www.mediafire.com/view/pcjva8zquzusatb/risc-v_register_file.png
(f) TLB
https://www.mediafire.com/view/erg2g8kten8g5s4/tlb00.jpg
https://www.mediafire.com/view/samtgj16larj92e/tlb01.jpg
https://www.mediafire.com/view/nnkv34bmkvxnfn9/tlb02.jpg
There are 2 parts in virtual address
VPN + page offset
There are 2 parts in VPN
tag + index
(TLB tag, TLB index)
There are 3 parts in TLB
valid + tag + PPN
Using index of VPN will find one line of TLB
If valid == 1 && (tag of vpn == tag of TLB) is hit
Get the PPN of TLB + page offset of virtual address is physical address
(g) Cache
https://www.mediafire.com/view/eoqpwahd3vjh4tn/tlb03.jpg
https://www.mediafire.com/view/gsuo1fxmlitlbd3/tlb04.jpg
https://www.mediafire.com/view/ysvfsz1arb0naxv/cache00.png
https://www.mediafire.com/view/y4vp2esxdgjiuft/cache01.png
There are 3 parts in physical address
tag + index + data offset
(cache tag , cache index, cache offset)
tag is PPN
index + data is page offset of virtual address
There are 2 parts in cache
valid + tag + block data
Using index of physical address will find one line of cache
If valid == 1 && (tag of physical address == tag of cache) is hit
Using data offset of physical address can find one byte of block data
Ex: cache 32k bytes as follows
tag = 20 bits
block data = 64 bytes
Number of Lines: 8 lines
Number of Sets: 64 sets
64 * 8 * 64 / 1024 = 32k
(1 set have 8 lines, each line have 64 bytes block data)
(h)
page table walker(PTW) of mmu
https://arxiv.org/pdf/2009.07723.pdf
https://www.mediafire.com/view/afmuwcipxetgozj/risc-v_ptw00.jpg
https://www.mediafire.com/view/9ghcqws59j4sjqh/risc-v_ptw01.jpg
io.requestor(0).req.xxx accept Dcache request
io.requestor(0).rep.xxx send addr/data to Dcache
io.requestor(1).req.xxx accept TLB request
io.requestor(1).rep.xxx send addr/data to TLB
ex:
when (io.req.fire() && tlb_miss)
r_refill_tag := vpn
and
io.ptw.req.bits.bits.addr := r_refill_tag
and
io.requestor(1).req.bits.bits.addr (PTW) := io.ptw.req.bits.bits.addr (TLB)
and
io_requestor_1_req_bits_bits_addr (arb) := io.requestor(1).req.bits.bits.addr (PTW)
(i)
extended instruction
in Chisel modify ALU.scala, Instructions.scala, IDecode.scala
and
modify riscv64 compiler source riscv-opc.h, riscv-opc.c that in directory riscv-binutils
https://www.bilibili.com/video/BV1Ph411d76Y
https://www.bilibili.com/video/BV1wV411S7Cg
(j)
chisel3 api search
https://www.chisel-lang.org/api/latest/chisel3/index.html
/////////////////////////////////////////////////////////////////////////////////////////////////////////
Tesla told in New York Herald: I prefer to be remembered as the inventor who succeeded in abolishing war. That will be my highest pride.
http://www.teslacollection.com/tesla_articles/1898/new_york_herald/f_l_christman/tesla_declares_he_will_abolish_war
(in middle section)
Albert Einstein: The release of atom power has changed everything except our way of thinking... the solution to this problem lies in the heart of mankind. If only I had known, I should have become a watchmaker.
https://atomictrauma.wordpress.com/the-scientists/albert-einstein
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