1. preinstall
apt install build-essential cmake clang bison flex libreadline-dev gawk tcl-dev libffi-dev git mercurial graphviz xdot pkg-config libftdi-dev qt5-default libboost-all-dev libeigen3-dev
apt install autoconf automake autotools-dev curl libmpc-dev libmpfr-dev libgmp-dev texinfo gperf libtool patchutils bc zlib1g-dev git libexpat1-dev
apt install libhidapi-dev libusb-1.0-0-dev
install python3.7 + pip3
refer to http://fatalfeel.blogspot.com/2019/12/ai-with-cuda-install-step-and-yolov3-in.html
2.
#install scala tool:
https://www.scala-sbt.org/download.html
echo "deb https://repo.scala-sbt.org/scalasbt/debian all main" | sudo tee /etc/apt/sources.list.d/sbt.list
echo "deb https://repo.scala-sbt.org/scalasbt/debian /" | sudo tee /etc/apt/sources.list.d/sbt_old.list
curl -sL "https://keyserver.ubuntu.com/pks/lookup?op=get&search=0x2EE0EA64E40A89B84B2DF73499E82A75642AC823" | sudo apt-key add
sudo apt update
sudo apt install sbt
3.
#download IntelliJ IDEA Community Edition 2019.3.5
https://www.jetbrains.com/idea/download/other.html
extract to /opt/idea-IC-193.7288.26
4.
cd $HOME
mkdir -p icesugar
cd $HOME/icesugar
git clone --recursive https://github.com/YosysHQ/icestorm.git
git clone --recursive https://github.com/cseed/arachne-pnr.git
git clone --recursive https://github.com/YosysHQ/nextpnr
git clone --recursive https://github.com/YosysHQ/yosys.git
git clone --recursive https://github.com/wuxx/icesugar.git
git clone --recursive https://github.com/verilator/verilator
5.
cd $HOME/icesugar/icestorm
make -j8
make install
cd $HOME/icesugar/arachne-pnr
make -j8
make install
cd $HOME/icesugar/nextpnr
cmake -DARCH=ice40 -DCMAKE_INSTALL_PREFIX=/usr/local .
make -j8
make install
cd $HOME/icesugar/yosys
make -j8
make install
cd $HOME/icesugar/verilator
autoconf
./configure
make -j8 && make install
6. riscv-gcc
cd $HOME/icesugar
git clone https://github.com/riscv/riscv-gnu-toolchain ###(no --recursive)
cd riscv-gnu-toolchain
git checkout 411d134
git submodule update --init --recursive
mkdir build
cd build
../configure --prefix=/opt/riscv32i --with-arch=rv32i --with-abi=ilp32
make -j8
note:
"M" Standard Extension for Integer Multiplication and Divison
"A" Standard Extension for Atomic Instructions
"F" Standard Extension for Single-Precision Floating-Point
"D" Standard Extension for Double-Precision Floating-Point
"Q" Standard Extension for Quard-Precision Floating-point
"C" Standard Extension for Compressed Instruction
"G" combination of I, M, A, F and D.
ilp32/ilp32f/ilp32d int-32bits long-32bits pointer-32bits
lp64/lp64f/lp64d int-32bits long-64bits pointer-64bits
7. icesprog
cd $HOME/riscv-cpu/icesugar/tools/src
make -j8
mkdir -p /opt/icesprog
cp -f ./icesprog /opt/icesprog
gedit /etc/environment
#add path
/opt/icesprog
reboot
8.
refer to https://fatalfeel.blogspot.com/2013/12/chisel-design-ic-for-risc-v.html
install sbt and IntelliJ IDEA
open $HOME/riscv-cpu/icesugar/src/basic/SpinalHDL/leds/leds
run test
////////////////////////VexRiscv////////////////////////
1.
gedit $HOME/riscv-cpu/icesugar/src/basic/SpinalHDL/leds/leds/burn.sh
#!/bin/sh -v
iceprog ./Test.bin
~in IntelliJ IDEA run burn.sh~
https://www.mediafire.com/view/rw68cxztdqyuqvv/burnbin.png
or
~in Terminal run burn.sh~
2.
gedit $HOME/riscv_cpu/icesugar/src/advanced/VexRiscv/src/main/c/murax/hello_world/makefile
SIFIVE_GCC_PACK ?= yes
~change to
SIFIVE_GCC_PACK=no
export PATH=$PATH:/opt/riscv32i/bin
export AR=riscv32-unknown-elf-ar
export AS=riscv32-unknown-elf-as
export CC=riscv32-unknown-elf-gcc
export CXX=riscv32-unknown-elf-g++
export LD=riscv32-unknown-elf-ld
cd $HOME/riscv-cpu/icesugar/src/advanced/VexRiscv/src/main/c/murax/hello_world
make
option: you can use this source substitute original hello_world
https://github.com/SpinalHDL/VexRiscvSocSoftware/tree/master/projects/murax/demo
3.
gedit $HOME/riscv-cpu/icesugar/src/advanced/VexRiscv/src/main/scala/vexriscv/demo/Murax.scala
/*SpinalVerilog(Murax(MuraxConfig.default.copy(onChipRamSize = 8 kB, onChipRamHexFile = "src/main/ressource/hex/muraxDemo.hex")))*/
SpinalVerilog(Murax(MuraxConfig.default.copy(onChipRamSize = 8 kB, onChipRamHexFile = "src/main/c/murax/hello_world/build/hello_world.hex")))
4.
IntelliJ IDEA open $HOME/riscv-cpu/icesugar/src/advanced/VexRiscv
right click [MuraxWithRamInit] in $HOME/riscv-cpu/icesugar/src/advanced/VexRiscv/src/main/scala/vexriscv/demo/Murax.scala
select run
~generate~
Murax.v
Murax.v_toplevel_system_ram_ram_symbol0.bin
Murax.v_toplevel_system_ram_ram_symbol1.bin
Murax.v_toplevel_system_ram_ram_symbol2.bin
Murax.v_toplevel_system_ram_ram_symbol3.bin
right click [LinuxGen] in $HOME/riscv-cpu/icesugar/src/advanced/VexRiscv/src/main/scala/vexriscv/demo/Linux.scala
select run
~generate~
VexRiscv.v (simulation only)
5.
(a)
#check VexRiscv/scripts/Murax/iCE40-hx8k_breakout_board/Makefile
gedit $HOME/riscv-cpu/icesugar/src/advanced/VexRiscv/compile_hx8k.sh
#!/bin/sh -v
yosys -v3 -p "synth_ice40 -top toplevel -blif toplevel.blif" ./Murax.v ./scripts/Murax/iCE40-hx8k_breakout_board/toplevel.v
arachne-pnr -p ./scripts/Murax/iCE40-hx8k_breakout_board/toplevel.pcf -d 8k --max-passes 600 -P ct256 ./toplevel.blif -o ./toplevel.asc
icepack ./toplevel.asc ./toplevel.bin
(b)
#check VexRiscv/scripts/Murax/iCESugar/Makefile
gedit $HOME/riscv-cpu/icesugar/src/advanced/VexRiscv/compile_up5k.sh
#!/bin/sh -v
yosys -v3 -p "synth_ice40 -top toplevel -blif toplevel.blif" ./Murax.v ./scripts/Murax/iCESugar/toplevel.v
arachne-pnr -p ./scripts/Murax/iCESugar/io.pcf -d 5k --max-passes 600 -P sg48 ./toplevel.blif -o ./toplevel.asc
icepack ./toplevel.asc ./toplevel.bin
~in IntelliJ IDEA run compile.sh~
https://www.mediafire.com/view/3qj0qss0v1i3iwz/makebin.png
or
~inTerminal run compile.sh~
https://www.mediafire.com/file/tl8gdiadc04jdn7/compile_ice40_hx8k.sh
https://www.mediafire.com/file/yfl3z8hzg60u8zk/compile_ice40_up5k.sh
https://www.mediafire.com/file/3xrozfflhe99e59/compile_vexriscv.sh
/////////////////////picorv32/////////////////////
Preinstall: icestorm, arachne-pnr, nextpnr, yosys, riscv-gcc
export PATH=$PATH:/opt/riscv32i/bin
export AR=riscv32-unknown-elf-ar
export AS=riscv32-unknown-elf-as
export CC=riscv32-unknown-elf-gcc
export CXX=riscv32-unknown-elf-g++
export LD=riscv32-unknown-elf-ld
#iCE40-HX8K
cd $HOME/riscv-cpu/icesugar/src/advanced/picorv32/scripts/icestorm
make -j8
cd $HOME/riscv-cpu/icesugar/src/advanced/picorv32/scripts/yosys
chmod 755 ./synth_osu018.sh
./synth_osu018.sh
cd $HOME/riscv-cpu/icesugar/src/advanced/picorv32/picosoc
make hx8kdemo_fw.bin
make icesugar.bin
/////////////////////litex-buildenv/////////////////////
1.
dpkg-reconfigure dash
select NO
2.
gedit $HOME/riscv-cpu/icesugar/src/advanced/litex-buildenv/third_party/litex/.gitmodules
url = https://git.llvm.org/git/compiler-rt
#change to
url = https://github.com/llvm-mirror/compiler-rt.git
3.
cd $HOME/riscv-cpu/icesugar/src/advanced/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv
rm -rf verilog
git clone https://github.com/litex-hub/pythondata-cpu-vexriscv.git verilog
(download-env.sh will checkout later)
4.
gedit $HOME/riscv-cpu/icesugar/src/advanced/litex-buildenv/Makefile
FIRMWARE_DIR = $(TARGET_BUILD_DIR)/software/$(FIRMWARE)
#change to
FIRMWARE_DIR = $(TARGET_BUILD_DIR)/software/stub
5.
export PLATFORM=ice40_hx8k_b_evn
#or
export PLATFORM=ice40_up5k_b_evn
export TARGET=base
export CPU=vexriscv
export FIRMWARE=linux
export CPU_VARIANT=min
#using VexRiscv_Min.v
cd $HOME/riscv-cpu/icesugar/src/advanced/litex-buildenv
./scripts/debian-setup.sh
./scripts/download-env.sh
7.
cd $HOME/riscv-cpu/icesugar/src/advanced/litex-buildenv
source ./scripts/enter-env.sh
conda install nextpnr-ice40=0.0.0_2427
make gateware -j8 V=1
make firmware -j8 V=1
make bios -j8 V=1
make image -j8 V=1
make gateware-flash
#or
make image-flash
Full source with patch:
https://www.mediafire.com/file/34k384pdflvfmwo/icesugar.tar.gz
Refer to:
1. http://www.clifford.at/icestorm
2. https://github.com/wuxx/icesugar
3. https://github.com/cliffordwolf/picorv32
4. https://github.com/SpinalHDL/VexRiscv
5. https://github.com/SpinalHDL/VexRiscvSocSoftware
6. https://pingu98.wordpress.com/2019/04/08/how-to-build-your-own-cpu-from-scratch-inside-an-fpga
7. https://github-wiki-see.page/m/timvideos/litex-buildenv/wiki/HowTo-FuPy-on-iCE40-Boards
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